The present invention relates generally to integrated circuits, and more particularly, to techniques and circuits for storing data in a static random access memory.
Static random access memory (SRAM) is used in many electronic systems to store digital data without the need for periodic refresh. For example, the cache memory of many computer systems is made up of SRAM. A typical SRAM cell fabricated in a metal-oxide-semiconductor (MOS) process with one read/write port is often made from six transistorsxe2x80x94four transistors to hold the data and two transistors per read/write port used as access devices. The access devices are typically controlled by xe2x80x9cword linesxe2x80x9d running in a first direction (for example, across a row or the horizontal direction when viewed oriented a certain way) and would dump/take data from xe2x80x9cbit linesxe2x80x9d running in another direction (for example, along a column or the vertical direction when viewed as described above). Therefore, a typical SRAM cell requires one word line running in the horizontal direction per row of SRAM cells and two bit lines running in the vertical direction per column of SRAM cells.
Some specialized applications, however, require an SRAM cell to have functionality in addition to a single read/write port. One such specialized application involves the storage of xe2x80x9cphysical hit vectorsxe2x80x9d as described in U.S. Pat. No. 6,014,732 granted to Naffziger which is hereby incorporated herein by reference. This application needs two read/write ports and the ability to clear an entire column of SRAM cells.
The addition of another read/write port and the ability to clear an entire column increases the number of word lines running horizontally and the number of bit lines running vertically. In particular, two additional bit lines running vertically for the second read/write port and a xe2x80x9cclearxe2x80x9d line also running vertically would be needed for each column of SRAM cells. Likewise, an additional word line would have to run horizontally across each row of SRAM cells. This brings the total number of lines running vertically over a given SRAM cell to five and the total number of lines running horizontally to two for a total of seven lines running across each SRAM cell.
This number of lines, especially lines running in the vertical direction, tends to grow the size of the SRAM cell significantly and reduce its frequency of operation. Accordingly, there is a need in the art for a two-ported SRAM cell with a column clear function that has fewer that five vertical lines and fewer that seven total lines across the cell.
The present invention provides an SRAM cell and array that has a column clear function with only three vertical lines and six total lines across a cell and a method of operating that cell and array of those cells. Instead of two bit lines per port and two access devices per port as in a traditional SRAM cell, one bit line and one access device per port are used. In addition, one additional bit line, one additional word line, and two devices in series are used to perform the column clear operation and complete a write operation.
The cell is operated by performing write operations using a two step process. To perform a write, each cell in a row to be written is preset during a first step. Then, each cell that is to have a zero written to it is cleared using the additional bit line and additional word line to address the cells to be cleared. A column of cells may be cleared by enabling all the rows for clearing, then asserting column clear control signals for each of the columns in the array to be cleared.
Other aspects and advantages of the present invention will become apparent from the following detailed description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention.